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1 astec semiconductor as384x current mode controller features 2.5 v bandgap reference trimmed to 1.0% and temperature-compensated standard temperature range extended to 105?c as3842/3 oscillations trimmed for precision duty cycle clamp as3844/5 have exact 50% max duty cycle clamp advanced oscillator design simplifies synchronization improved specs on uvlo and hysteresis provide more predictable start-up and shutdown improved 5 v regulator provides better ac noise immunity guaranteed performance with current sense pulled below ground description the as3842 family of control ics provide pin-for-pin replacement of the industry standard uc3842 series of devices. the devices are redesigned to provide significantly improved tolerances in power sup- ply manufacturing. the 2.5 v reference has been trimmed to 1.0% tolerance. the oscillator discharge current is trimmed to provide guar- anteed duty cycle clamping rather than specified discharge current. the circuit is more completely specified to guarantee all parameters impacting power supply manufacturing tolerances. in addition, the oscillator and flip-flop sections have been enhanced to provide additional performance. the r t /c t pin now doubles as a syn- chronization input that can be easily driven from open collector/open drain logic outputs. this sync input is a high impedance input and can easily be used for externally clocked systems. the new flip-flop topol- ogy allows the duty cycle on the as3844/5 to be guaranteed between 49 and 50%. the as3843/5 requires less than 0.5 ma of start-up cur- rent over the full temperature range. semiconductor pin configuration ? top view 14l soic (d14) 8l soic (d8) 1 2 3 4 8 7 6 5 v reg v cc out gnd comp v fb i sense r t /c t v reg nc v cc v c comp nc v fb out pwr g gnd i sense nc r t /c t nc pdip (n) v reg v cc out gnd comp v fb i sense r t /c t 1 2 3 4 8 7 6 5 1 2 3 5 6 7 4 14 13 12 11 10 9 8 circuit type: current mode controller (see table a) package style d8 = d14 = n = 8 14 8 pin plastic soic pin plastic soic pin plastic dip as384x d8 13 packaging option: t 13 = tube = tape and reel (13" reel dia) ordering information table a duty cycle model v cc(min) v cc(on) typ. i cc as3842 10 16 97% 0.5 ma as3843 7.6 8.4 97% 0.3 ma as3844 10 16 49.5% 0.5 ma as3845 7.6 8.4 49.5% 0.3 ma
2 astec semiconductor as384x current mode controller functional block diagram figure 1. block diagram of the as3842/3/4/5 pin function description pin number function description 1 comp this pin is the error amplifier output. t ypically used to provide loop compensation to maintain v fb at 2.5 v . 2 v fb inverting input of the error amplifier . the non-inverting input is a trimmed 2.5 v bandgap reference. 3 current a voltage proportional to inductor current is connected to the input. the pwm uses sense this information to terminate the gate drive of the output. 4 r t /c t oscillator frequency and maximum output duty cycle are set by connecting a resistor (r t ) to v reg and a capacitor (c t ) to ground. pulling this pin to ground or to v reg will accomplish a synchronization function. 5 gnd circuit common ground, power ground, and ic substrate. 6 output this output is designed to directly drive a power mosfet switch. this output can sink or source peak currents up to 1a. the output for the as3844/5 switches at one-half the oscillator frequency . 7 v cc positive supply voltage for the ic. 8 v reg this 5 v regulated output provides charging current for the capacitor c t through the resistor r t . e + e + e + e + 6 output 2 error amp 1 4 5 7 8 gnd v cc v reg current sense r t /c t v fb comp s r ff s r ff (5.0 v) (2.5 v) (1.0 v) 2r r (5 v) (3.0 v) (1.3 v) (0.6 v) oscilla tor pwm comp ara tor over tempera ture t ff clk 2 [3844/45] clk [3842/43] 5 v regula tor (5.0 v) ref ok (4 v) uvlo (6 v) pwm logic 3 + e
3 astec semiconductor as384x current mode controller absolute maximum ratings parameter symbol rating unit supply v oltage (i cc < 30 ma) v cc self-limiting v supply v oltage (low impedance source) v cc 30 v output current i out 1 a output energy (capacitive load) 5 j analog inputs (pin 2, pin 3) e0.3 to 30 v error amp sink current 10 ma maximum power dissipation p d 8l soic 750 mw 8l pdip 1000 mw 14l soic 950 mw maximum junction t emperature t j 150 ? c operating t emperature 0 to 150 ? c storage t emperature range t stg e65 to 150 ? c lead t emperature, soldering 10 seconds t l 300 ? c stresses greater than those listed under absolute maximum ra tings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above indicated in the operational s ections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may af fect reliability . recommended conditions parameter symbol rating unit supply v oltage v cc as3842,4 15 v as3843,5 10 v oscillator f osc 50 to 500 khz t ypical thermal resistances package q ja q jc t ypical derating 8l pdip 95 ? c/w 50 ? c/w 10.5 mw/ ? c 8l soic 175 ? c/w 45 ? c/w 5.7 mw/ ? c 14l soic 130 ? c/w 35 ? c/w 7.7 mw/ ? c
4 astec semiconductor as384x current mode controller electrical characteristics electrical characteristics are guaranteed over full junction temperature range (0 to 105 ? c). ambient temperature must be derated based on power dissipation and package thermal characteristics. the conditions are: v cc = 15 v , r t = 10 k ? , and c t = 3.3 nf , unless otherwise stated. t o override uvlo, v cc should be raised above 17 v prior to test. parameter symbol t est condition min. t yp. max. unit 5 v regulator output v oltage v reg t j = 25 ? c, i reg = 1 ma 4.95 5.00 5.05 v line regulation psrr 12 2 v cc 2 25 v 2 10 mv load regulation 1 2 i reg 2 20 ma 2 10 mv t emperature stability 1 tc reg 0.2 0.4 mv/ ? c t otal output v ariation 1 line, load, temperature 4.85 5.15 v long-term stability 1 over 1,000 hrs at 25 ? c 5 25 mv output noise v oltage v noise 10 hz 2 f 2 100 khz, t j = 25 ? c 50 v short circuit current i sc 30 100 180 ma 2.5 v internal reference nominal v oltage v fb t = 25 ? c; i reg = 1 ma 2.475 2.500 2.525 v line regulation psrr 12 v 2 v cc 2 25 v 2 5 mv load regulation 1 2 i reg 2 20 ma 2 5 mv t emperature stability 1 tc vfb 0.1 0.2 mv/ ? c t otal output v ariation 1 line, load, temperature 2.450 2.500 2.550 v long-term stability 1 over 1,000 hrs at 125 ? c 2 12 mv oscillator initial accuracy f osc t j = 25 ? c 47 52 57 khz v oltage stability 12 v 2 v cc 2 25 v 0.2 1 % t emperature stability 1 tc f t min 2 t j 2 t max 5 % amplitude f osc v r t/ct peak-to-peak 1.6 v upper t rip point v h 2.9 v lower t rip point v l 1.3 v sync threshold v sync 400 600 800 mv discharge current i d 7.5 8.7 9.5 ma duty cycle limit r t = 680 ? , c t = 5.3 nf , t j = 25 ? c 46 50 52 %
5 astec semiconductor as384x current mode controller electrical characteristics (cont?d) electrical characteristics are guaranteed over full junction temperature range (0 to 105 ? c). ambient temperature must be derated based on power dissipation and package thermal characteristics. the conditions are: v cc = 15 v , r t = 10 k ? , and c t = 3.3 nf , unless otherwise stated. t o override uvlo, v cc should be raised above 17 v prior to test. parameter symbol t est condition min. t yp. max. unit error amplifier input v oltage v fb t j = 25 ? c 2.475 2.500 2.525 v input bias current i bias e0.1 e1 a v oltage gain a vol 2 2 v comp 2 4 v 65 90 1 db t ransconductance g m 1 ma/mv unity gain bandwidth 1 gbw 0.8 1.2 mhz power supply rejection ratio psrr 12 2 v cc 2 25 v 60 70 db output sink current i compl v fb = 2.7 v , v comp = 1.1 v 2 6 ma output source current i comph v fb = 2.3 v , v comp = 5 v 0.5 0.8 ma output swing high v comph v fb = 2.3 v , r l = 15 k ? to ground 5 5.5 v output swing low v compl v fb = 2.7 v , r l = 15 k ? to pin 8 0.7 1.1 v current sense comparator t ransfer gain 2,3 a v cs e0.2 2 v sense 2 0.8 v 2.85 3.0 3.15 v/v i sense level shift 2 v ls v sense = 0 v 1.5 v maximum input signal 2 v comp = 5 v 0.9 1 1.1 v power supply rejection ratio psrr 12 2 v cc 2 25 v 70 db input bias current i bias e1 e10 a propagation delay to output 1 t pd 85 150 ns output output low level v ol i sink = 20 ma 0.1 0.4 v v ol i sink = 200 ma 1.5 2.2 v output high level v oh i source = 20 ma 13 13.5 v v oh i source = 200 ma 12 13.5 v rise t ime 1 t r c l = 1 nf 50 150 ns fall t ime 1 t f c l = 1 nf 50 150 ns housekeeping start-up threshold v cc (on) 3842/4 15 16 17 v 3843/5 7.8 8.4 9.0 v minimum operating v oltage v cc (min) 3842/4 9 10 1 1 v after t urn on 3843/5 7.0 7.6 8.2 v output low level in uv state v ouv i sink = 20 ma, v cc = 6 v 1.5 2.0 v over-t emperature shutdown 4 t ot 125 ? c
6 astec semiconductor as384x current mode controller electrical characteristics (cont?d) electrical characteristics are guaranteed over full junction temperature range (0 to 105 ? c). ambient temperature must be derated based on power dissipation and package thermal characteristics. the conditions are: v cc = 15 v , r t = 10 k ? , and c t = 3.3 nf , unless otherwise stated. t o override uvlo, v cc should be raised above 17 v prior to test. parameter symbol t est condition min. t yp. max. unit pwm maximum duty cycle d max 3842/3 94 97 100 % minimum duty cycle d min 3842/3 0 % maximum duty cycle d max 3844/5 49 49.5 50 % minimum duty cycle d min 3844/5 0 % supply current start-up current i cc 3842/4, v fb = v sense = 0 v , v cc = 14 v 0.5 1.0 ma 3843/5, v fb = v sense = 0 v , v cc = 7 v 0.3 0.5 ma operating supply current i cc 9 17 ma v cc zener v oltage v z i cc = 25 ma 30 v notes: 1. this parameter is not 100% tested in production. 2. parameter measured at trip point of pwm latch. 3. t ransfer gain is the relationship between current sense input and corresponding error amplifier output at the pwm latch trip poi nt and is mathematically expressed as follows: 4. at the over-temperature threshold, t ot , the oscillator is disabled. the 5 v reference and the pwm stages, including the pwm latch, remain powered. = e a i v v comp sense d d ; 0.2 v 0.8 sense
7 astec semiconductor as384x current mode controller t ypical performance curves figure 2 figure 4 figure 3 figure 5 0 5 10 15 v cc ?supply v oltage (v) 20 25 35 30 supply current vs supply v oltage 0 5 10 15 20 25 i cc ?supply current (ma) as3843/5 as3842/4 0 5 10 15 v cc ?supply v oltage (v) 20 25 30 0 5 10 15 20 25 as3843/5 as3842/4 output v oltage vs supply v oltage v out ?output v oltage (v) t a ?ambient t emperature ( c) ?0 ?0 0 30 60 90 120 150 5.04 5.02 5.00 4.98 4.96 4.94 4.92 4.90 regulator output v oltage vs ambient t emperature v reg ?regulator output (v) t a ?ambient t emperature ( c) ?0 ?0 0 30 60 90 120 150 160 140 120 100 80 60 40 regulator short circuit current vs ambient t emperature i reg ?regulator short cir cuit (ma)
8 astec semiconductor as384x current mode controller t ypical performance curves figure 6 figure 8 figure 7 figure 9 0 20 40 60 80 100 120 140 i sc ?regulator sour ce current (ma) 0 ? ? ?2 ?6 ?0 ?4 regulator load regulation d v reg ?regulator v oltage change (mv) 150 c 25 c ?5 c 0.3 1 r t ?t iming register (k w ) 3 10 20 40 60 80 100 maximum duty cycle (%) maximum duty cycle vs t iming resistor 10 100 1 m 100 10 1 0.1 c t ?t iming capacitor (nf) t iming capacitor vs oscillator frequency f osc ?oscillator frequency (khz) r t = 680 w r t = 1 k w r t = 2.2 k w r t = 4.7 k w r t = 10 k w t a ?ambient t emperature ( c) ?5 ?5 ?5 5 25 45 65 85 105 125 100 90 80 70 60 50 40 maximum duty cycle (%) maximum duty cycle t emperature stability r t = 10 k w r t = 2.2 k w r t = 1 k w r t = 680 w
9 astec semiconductor as384x current mode controller t ypical performance curves figure 10 figure 12 figure 1 1 figure 13 0 1 2 3 4 5 6 1.2 1.0 0.8 0.6 0.4 0.2 0 ?.2 ?.4 v sense ?current sense input threshold (v) current sense input threshold vs error amp output v oltage t a = 125 c t a = 25 c t a = ?5 c v comp ?error amp output v oltage (v) ?0 ?0 0 30 60 t a ?ambient t emperature ( c) 90 120 15 2.46 2.47 2.48 2.49 2.50 2.51 v fb = v comp v cc = 15 v v fb ?error amp input v oltage (v) error amp input v oltage vs ambient t emperature 0 0.5 1.0 1.5 2.0 2.5 1 a 100 10 1 i out _ output sink current (ma) output sink capability in under -v oltage mode v out ?output v oltage (v) v cc = 6 v t a = 25 c 10 100 i out ?output saturation current (ma) 500 0 1 2 3 ? ? 0 output saturation v oltage v sa t ?output saturation v oltage (v) sour ce saturation v out ?v cc t j = 125 c sink saturation t j = 125 c t j = ?5 c t j = 25 c
10 astec semiconductor application information the as3842/3/4/5 family of current-mode control ics are low cost, high performance controllers which are pin compatible with the industry stan - dard uc3842 series of devices. suitable for many switch mode power supply applications, these ics have been optimized for use in high frequency of f-line and dc-dc converters. the as3842 has been enhanced to provide signifi - cantly improved performance, resulting in excep - tionally better tolerances in power supply manufacturing. in addition, all electrical charac - teristics are guaranteed over the full 0 to 105 ? c temperature range. among the many enhance - ments are: a precision trimmed 2.5 volt reference (+/e 1% of nominal at the error amplifier input), a significantly reduced propagation delay from cur - rent sense input to the ic output, a trimmed oscil - lator for precise duty-cycle clamping, a modified flip-flop scheme that gives a true 50% duty ratio clamp on 3844/45 types, and an improved 5 v regulator for better ac noise immunity . further - more, the as3842 provides guaranteed perfor - mance with current sense input below ground. the advanced oscillator design greatly simplifies synchronization. the device is more completely specified to guarantee all parameters that impact power supply manufacturing tolerances. section 1 e theory of operation the functional block diagram of the as3842 is shown in figure 1. the ic is comprised of the six basic functions necessary to implement current mode control; the under-voltage lockout; the refer - ence; the oscillator; the error amplifier; the current sense comparator/pwm latch; and the output. the following paragraphs will describe the theory of operation of each of the functional blocks. 1.1 under-voltage lockout (uvlo) the under-voltage lockout function of the as3842 holds the ic in a low quiescent current ( 2 1 ma) standby mode until the supply voltage (v cc ) exceeds the upper uvlo threshold volt - age. this guarantees that all of the ic? s internal circuitry are properly biased and fully functional before the output stage is enabled. once the ic turns on, the uvlo threshold shifts to a lower level (hysteresis) to prevent v cc oscillations. the low quiescent current standby mode of the as3842 allows bootstrappinge?a technique used in of f-line converters to start the ic from the rectified ac line voltage initially , after which power to the ic is provided by an auxiliary winding of f the power supply? s main transformer . figure 14 shows a typical bootstrap circuit where capacitor (c) is as384x current mode controller + r < v dc min 1 ma r + >1 ma 16 v/10 v (3842/4) 8.4 v/7.8 v (3843/5) out 6 ic enable ac line c as384x 7 v cc 5 gnd aux pri sec v dc figure 14. bootstrap circuit
11 astec semiconductor charged via resistor (r) from the rectified ac line. when the voltage on the capacitor (v cc ) reaches the upper uvlo threshold, the ic (and hence, the power supply) turns on and the voltage on c begins to quickly discharge due to the increased operating current. during this time, the auxiliary winding begins to supply the current necessary to run the ic. the capacitor must be suf ficiently large to maintain a voltage greater than the lower uvlo threshold during start-up. the value of r must be selected to provide greater than 1 ma of current at the minimum dc bus voltage (r < vdcmin/1 ma). the uvlo feature of the as3842 has significant advantages over standard 3842 devices. first, the uvlo thresholds are based on a temperature compensated bandgap reference rather than con - ventional zeners. second, the uvlo disables the output at power down, of fering additional protec - tion in cases where v reg is heavily decoupled. the uvlo on some 3842 devices shuts down the 5 volt regulator only , which results in eventual power down of the output only after the 5 volt rail collapses. this can lead to unwanted stresses on the switching devices during power down. the as3842 has two separate comparators which monitor both v cc and v ref and hold the output low if either are not within specification. the as3842 family of fers two dif ferent uvlo options. the as3842/4 has uvlo thresholds of 16 volts (on) and 10 volts (of f). the as3843/5 has uvlo levels of 8.4 volts (on) and 7.6 volts (of f). 1.2 reference (v reg and v fb ) the as3842 ef fectively has two precise bandgap based temperature compensated voltage refer - ences. most obvious is the v reg pin (pin 8) which is the output of a series pass regulator . this 5.0 v output is normally used to provide charging cur - rent to the oscillator ? s timing capacitor (section 1.3). in addition, there is a trimmed internal 2.5 v reference which is connected to the non-inverting (+) input of the error amplifier . the tolerance of the internal reference is 1% over the full speci - fied temperature range, and 1% for v reg. the reference section of the as3842 is greatly improved over the standard 3842 in a number of ways. for example, in a closed loop system, the voltage at the error amplifier ? s inverting input (v fb , pin 1) is forced by the loop to match the voltage at the non-inverting input. thus, v fb is the voltage which sets the accuracy of the entire system. the 2.5 v reference of the as3842 is tightly trimmed for precision at v fb , including errors caused by the op amp, and is specified over temperature. this method of trim provides a precise reference voltage for the error amplifier while maintaining the original 5 v regulator specifications. in addi - tion, force/sense (kelvin) bonding to the package pin is utilized to further improve the 5 v load reg - ulation. standard 3842s, on the other hand, spec - ify tight regulation for the 5 v output only and rate it over line, load and temperature. the voltage at v fb , which is of critical importance, is loosely specified and only at 25 ? c. the reference section, in addition to providing a precise dc reference voltage, also powers most of the ic? s internal circuitry . switching noise, therefore, can be internally coupled onto the ref - erence. w ith this in mind, all of the logic within the as3842 was designed with ecl type circuitry which generates less switching noise because it runs at essentially constant current regardless of logic state. this, together with improved ac noise rejection, results in substantially less switching noise on the 5 v output. the reference output is short circuit protected and can safely deliver more than 20 ma to power external circuitry . 1.3 oscillator the newly designed oscillator of the as3842 is enhanced to give significantly improved perfor - mance. these enhancements are discussed in as384x current mode controller
12 astec semiconductor the following paragraphs. the basic operation of the oscillator is as follows: a simple rc network is used to program the fre - quency and the maximum duty ratio of the as3842 output. see figure 15. t iming capacitor (c t ) is charged through timing resistor (r t ) from the fixed 5.0 v at v reg . during the charging time, the out (pin 6) is high. assuming that the output is not terminated by the pwm latch, when the voltage across c t reaches the upper oscillator trip point ( ? 3.0 v), an internal current sink from pin 4 to ground is turned on and discharges c t towards the lower trip point. during this dis - charge time, an internal clock pulse blanks the output to its low state. when the voltage across c t reaches the lower trip point ( ? 1.3 v), the cur - rent sink is turned of f, the output goes high, and the cycle repeats. since the output is blanked during the discharge of c t , it is the discharge time which controls the output deadtime and hence, the maximum duty ratio. the nature of the as3842 oscillator circuit is such that, for a given frequency , many combinations of r t and c t are possible. however , only one value of r t will yield the desired maximum duty ratio at a given frequency . since a precise maximum duty ratio clamp is critical for many power supply designs, the oscillator discharge current is trimmed in a unique manner which provides sig - nificantly improved tolerances as explained later in this section. in addition, the as3844/5 options have an internal flip-flop which ef fectively blanks every other output pulse (the oscillator runs at twice the output frequency), providing an absolute maximum 50% duty ratio regardless of discharge time. 1.3.1 selecting timing components r t and c t the values of r t and c t can be determined mathematically by the following expressions: (1) as384x current mode controller 5 v reg oscillator as3842 6 output 7 v cc 8 r t c t i d 5 gnd clock pwm c t output large r t /small c t c t output small r t / large c t 4 figure 15. oscillator set-up and w aveforms c d r r t t t = | ? ? ? ? = | osc l h osc k k ln 1.63d
13 astec semiconductor (2) (3) (4) where f osc is the oscillator frequency , d is the maximum duty ratio, v h is the oscillator ? s upper trip point, v l is the lower trip point, v r is the ref - erence voltage, i d is the discharge current. t able 1 lists some common values of r t and the corresponding maximum duty ratio. t o select the timing components; first, use t able 1 or equation (2) to determine the value of r t that will yield the desired maximum duty ratio. then, use equation (1) to calculate the value of c t . for example, for a switching frequency of 250 khz and a maxi - mum duty ratio of 50%, the value of r t , from t able 1, is 683 ? . applying this value to equation (1) and solving for c t gives a value of 4700 pf . in practice, some fine tuning of the initial values may be necessary during design. however , due to the advanced design of the as3842 oscillator , once the final values are determined, they will yield repeatable results, thus eliminating the need for additional trimming of the timing compo - nents during manufacturing. 1.3.2 oscillator enhancements the as3842 oscillator is trimmed to provide guaranteed duty ratio clamping. this means that the discharge current (i d ) is trimmed to a value that compensates for all of the tolerances within the device (such as the tolerances of v reg , prop - agation delays, the oscillator trip points, etc.) which have an ef fect on the frequency and max - imum duty ratio. for example, if the combined tolerances of a particular device are 0.5% above nominal, then i d is trimmed to 0.5% above nomi - nal. this method of trimming virtually eliminates the need to trim external oscillator components during power supply manufacturing. standard 3842 devices specify or trim only for a specific value of discharge current. this makes precise as384x current mode controller t able 1. r t vs maximum duty ratio r t ( ? ) dmax 470 22% 560 37% 683 50% 750 54% 820 58% 910 63% 1,000 66% 1,200 72% 1,500 77% 1,800 81% 2,200 85% 2,700 88% 3,300 90% 3,900 91% 4,700 93% 5,600 94% 6,800 95% 8,200 96% 10,000 97% 18,000 98% r v i t reg d = (k l ) d 1e d e (k h ) d 1e d (k l ) d 1 e (k h ) d 1 k v h reg = - ? v v h h 0.432 ( k v l reg = - ? v v l reg 0.736 d d = - 1e d 1e d 582 (0.432) (0.736) d d - 1 1 (0.432) (0.736)
14 astec semiconductor and repeatable duty ratio clamping virtually impossible due to other ic tolerances. the as3844/5 provides true 50% duty ratio clamping by virtue of excluding from its flip-flop scheme, the normal output blanking associated with the discharge of c t . standard 3844/5 devices include the output blanking associated with the discharge of c t , resulting in somewhat less than a 50% duty ratio. 1.3.3 synchronization the advanced design of the as3842 oscillator simplifies synchronizing the frequency of two or more devices to each other or to an external clock. the r t /c t doubles as a synchronization input which can easily be driven from any open collector logic output. figure 16 shows some simple circuits for implementing synchronization. 1.4 error amplifier (comp) the as3842 error amplifier is a wide bandwidth, internally compensated operational amplifier which provides a high dc open loop gain (90 db). the input to the amplifier is a pnp dif feren - tial pair . the non-inverting (+) input is internally connected to the 2.5 v reference, and the invert - ing (e) input is available at pin 2 (v fb ). the out - put of the error amplifier consists of an active pull-down and a 0.8 ma current source pull-up as shown in figure 17. this type of output stage allows easy implementation of soft start, latched shutdown and reduced current sense clamp functions. it also permits wire or - ing of the error amplifier outputs of several 3842s, or com - plete bypass of the error amplifier when its output is forced to remain in its pull-up condition. as384x current mode controller + compensation network 2.50 v to pwm e/a 1 comp v fb 2 0.8 ma v out figure 17. error amplifier compensation v reg as3842 r t /c t gnd 8 4 r t c t 5 open collector output 5 v r t /c t open collector output 3 k 2 k 2 k r t /c t 3 k cmos sync external clock figure 16. synchronization
15 astec semiconductor in most typical power supply designs, the con - verter ? s output voltage is divided down and moni - tored at the error amplifier ? s inverting input, v fb . a simple resistor divider network is used and is scaled such that the voltage at v fb is 2.5 v when the converter ? s output is at the desired voltage. the voltage at v fb is then compared to the inter - nal 2.5 v reference and any slight dif ference is amplified by the high gain of the error amplifier . the resulting error amplifier output is level shifted by two diode drops and is then divided by three to provide a 0 to 1 v reference (v e ) to one input of the current sense comparator . the level shifting reduces the input voltage range of the current sense input and prevents the output from going high when the error amplifier output is forced to its low state. an internal clamp limits v e to 1.0 v . the purpose of the clamp is discussed in section 1.5. 1.4.1 loop compensation loop compensation of a power supply is neces - sary to ensure stability and provide good line/load regulation and dynamic response. it is normally provided by a compensation network connected between the error amplifier ? s output (comp) and inverting input as shown in figure 17. the type of network used depends on the converter topology and in particular , the characteristics of the major functional blocks within the supply ? i.e. the error amplifier , the modulator/switching circuit, and the output filter . in general, the network is designed such that the converter ? s overall gain/phase response approaches that of a single pole with a e20 db/decade rollof f, crossing unity gain at the highest possible frequency (up to f sw /4) for good dynamic response, with adequate phase margin (> 45 ? ) to ensure stability . figure 18 shows the gain/phase response of the error amplifier . the unity gain crossing is at 1.2 mhz with approximately 57 ? c of phase mar - gin. this information is useful in determining the configuration and characteristics required for the compensation network. one of the simplest types of compensation net - works is shown in figure 19. an rc network pro - vides a single pole which is normally set to compensate for the zero introduced by the output capacitor ? s esr. the frequency of the pole (f p ) is determined by the formula; (5) as384x current mode controller 10 1 10 2 10 3 10 4 10 5 10 6 10 7 ?0 0 20 40 60 80 240 210 180 150 120 90 60 30 0 ?0 ?0 frequency (hz) gain phase phase (degrees) gain (db) v out r i r bias 2.50 v t o pwm c f r f + e e/a figure 18. gain/phase response of the as3842 figure 19. a t ypical compensation network | p = 1 2 p r | c |
16 astec semiconductor resistors r 1 and r f set the low frequency gain and should be chosen to provide the highest pos - sible gain, without exceeding the unity gain cross - ing frequency limit of f s w /4. r bias , in conjunction with r 1 , sets the converter ? s output voltage; but has no ef fect on the loop gain/phase response. there are a few converter design considerations associated with the error amplifier . first, the val - ues of the divider network (r 1 and r bias ) should be kept low in order to minimize errors caused by the error amplifier ? s input bias current. an output voltage error equal to the product of the input bias current and the equivalent divider resis - tance, can be quite significant with divider values greater than 5 k ? . low divider resistor values also help to improve the noise immunity of the sensitive v fb input. the second consideration is that the error ampli - fier will typically source only 0.8 ma; thus, the value of feedback resistance (r f ) should be no lower than 5 k ? in order to maintain the error amplifier ? s full output range. in practice, however , the feedback resistance required is usually much greater than 5 k ? , hence this limitation is nor - mally not a problem. some power supply topologies may require a more elaborate compensation network. for example, flyback and boost converters operating with continuous current have transfer functions that include a right half plane (rhp) zero. these types of systems require an additional pole ele - ment within the compensation network. a detailed discussion of loop compensation, how - ever , is beyond the scope of this application note. 1.5 i sense current comparator/pwm latch the current sense comparator (sometimes called the pwm comparator) and accompanying latch circuitry make up the pulse width modula - tor (pwm). it provides pulse-by-pulse current sensing/limiting and generates a variable duty ratio pulse train which controls the output voltage of the power supply . included is a high speed comparator followed by ecl type logic circuitry which has very low propagation delays and switching noise. this is essential for high fre - quency power supply designs. the comparator has been designed to provide guaranteed perfor - mance with the current sense input below ground. the pwm latch ensures that only one pulse is allowed at the output for each oscillator period. the inverting input to the current sense com - parator is internally connected to the level shifted output of the error amplifier (v e ) as discused in the previous section. the non-inverting input is the i sense input (pin 3). it monitors the switched inductor current of the converter . figure 20 shows the current sense/pwm circuitry of the as3842, and associated waveforms. the output is set high by an internal clock pulse and remains high until one of two conditions occurs; 1) the oscillator times out (section 1.3) or 2) the pwm latch is set by the current sense compara - tor . during the time when the output is high, the converter ? s switching device is turned on and current flows through resistor r s . this produces a stepped ramp waveform at pin 3 as shown in figure 20. the current will continue to ramp up until it reaches the level of v e at the inverting input. at that point, the comparator ? s output goes high, setting the pwm latch and the output pulse is then terminated. thus, v e is a variable refer - ence for the current sense comparator , and it controls the peak current sensed by r s on a cycle-by-cycle basis. v s varies in proportion to changes in the input voltage/current (inner con - trol loop) while v e varies in proportion to changes in the converter ? s output voltage/current (outer control loop). the two control loops merge at the current sense comparator , producing a variable duty ratio pulse train that controls the output of the converter . as384x current mode controller
17 astec semiconductor the current sense comparator ? s inverting input is internally clamped to a level of 1.0 v to provide a current limit (or power limit for multiple output supplies) function. the value of r s is selected to produce 1.0 v at the maximum allowed current. for example, if 1.5 a is the maximum allowed peak inductor current, then r s is selected to equal 1 v/1.5 a = 0.66 ? . in high power applica - tions, power dissipation in the current sense resistor may become intolerable. in such a case, a current transformer can be used to step down the current seen by the sense resistor . see figure 21. 1.6 output (out) the output stage of the as3842 is a high current totem-pole configuration that is well suited for directly driving power mosfet s. it is capable of sourcing and sinking up to 1 a of peak current. cross conduction losses in the output stage have been minimized resulting in lower power dissipa - tion in the device. this is particularly important for high frequency operation. during under- voltage shutdown conditions, the output is active low . this eliminates the need for an external pull - down resistor . 1.7 over-temperature shutdown the as3842 has a built-in over-temperature shutdown which will limit the die temperature to 130 ? c typically . when the over-temperature con - dition is reached, the oscillator is disabled. all other circuit blocks remain operational. there - fore, when the oscillator stops running, output pulses terminate without losing control of the supply or losing any peripheral functions that may be running of f the 5 v regulator . the output may go high during the final cycle, but the pwm as384x current mode controller e + e + ff s r 5 v reg 2r r r s comp as3842/3/4/5 error amp 2.5 v v fb 1 v 1 2 3 rt/ct 4 v s r c leading edge filter clock pwm comparator v e v reg v cc output 8 7 6 5 gnd current sense clock output v e v s i s pri sec v in pwm logic figure 20. current sense/pwm latch circuit and w aveforms r s v s = r s i s v s n:1 i s n figure 21. optional current t ransformer
18 astec semiconductor latch is still fully operative, and the normal termi - nation of this cycle by the current sense com - parator will latch the output low until the over-temperature condition is rectified. cycling the power will reset the over-temperature disable mechanism, or the chip will re-start after cooling through a nominal hysteresis band. section 2 e design considerations 2.1 leading edge filter the current sensed by r s contains a leading edge spike as shown in figure 20. this spike is caused by parasitic elements within the circuit including the interwinding capacitance of the power transformer and the recovery characteris - tics of the rectifier diode(s). the spike, if not prop - erly filtered, can cause stability problems by prematurely terminating the output pulse. a simple rc filter is used to suppress the spike. the time constant should be chosen such that it approximately equals the duration of the spike. a good choice for r 1 is 1 k ? , as this value is opti - mum for the filter and at the same time, it simpli - fies the determination of r slope (section 2.2). if the duration of the spike is, for example, 100 ns, then c is determined by: (6) 2.2 slope compensation current-mode controlled converters can experi - ence instabilities or subharmonic oscillations as384x current mode controller t 0 d 1 d 2 t 1 i pk v e i l 2 i l 1 i avg 2 i avg 1 m 1 m 2 (a) t 0 d 1 d 2 t 1 v e d i m 1 m 2 (b) d i' t 0 d 1 d 2 t 1 v comp i l 2 i l 1 i avg 1 = i avg 2 m 1 m 2 (c) m = m 2 /2 t 0 d 1 d 2 t 1 d i m 1 m 2 (d) d i' v comp m = m 2 /2 figure 22. slope compensation c = = = time constant k ns k pf 1 100 1 100 w w
19 astec semiconductor when operated at duty ratios greater than 50%. t wo dif ferent phenomena can occur as shown graphically in figure 22. first, current-mode controllers detect and control the peak inductor current, whereas the con - verter ? s output corresponds to the average induc - tor current. figure 22(a) clearly shows that the average inductor current (i 1 & i 2 ) changes as the duty ratio (d 1 & d 2 ) changes. note that for a fixed control voltage, the peak current is the same for any duty ratio. the dif ference between the peak and average currents represents an error which causes the converter to deviate from true current-mode control. second, figure 22(b) depicts how a small pertur - bation of the inductor current ( ? i) can result in an unstable condition. for duty ratios less than 50%, the disturbance will quickly converge to a steady state condition. for duty ratios greater than 50%, ? i progressively increases on each cycle, caus - ing an unstable condition. both of these problems are corrected simultane - ously by injecting a compensating ramp into either the control voltage (v e ) as shown in figure 22(c) & (d), or to the current sense waveform at pin 3. since v e is not directly accessible, and, a positive ramp waveform is readily available from the oscillator at pin 4, it is more practical to add the slope compensation to the current waveform. this can be implemented quite simply with the addition of a single resistor , r slope , between pin 4 and pin 3 as shown in figure 23(a). r slope , in conjunction with the leading edge filter resistor , r 1 (section 2.1), forms a divider network which determines the amount of slope added to the waveform. the amount of slope added to the cur - rent waveform is inversely proportional to the value of r slope . it has been determined that the amount of slope (m) required is equal to or greater than 1/2 the downslope (m 2 ) of the induc - tor current. mathematically stated: (7) in some cases the required value of r slope may be low enough to af fect the oscillator circuit and thus cause the frequency to shift. an emitter fol - lower circuit can be used as a buf fer for r slope as depicted in figure 23(b). slope compensation can also be used to improve noise immunity in current mode converters oper - ating at less than 50% duty ratio. power supplies operating under very light load can experience as384x current mode controller r slope i sense r 1 i s r s r t 8 4 v reg r t /c t as3842 3 5 gnd c t r slope i sense r 1 i s r s r t 8 4 v reg r t /c t as3842 3 5 gnd c t (a) (b) optional buffer figure 23. slope compensation m 3 m 2 2
20 astec semiconductor instabilities caused by the low amplitude of the current sense ramp waveform. in such a case, any noise on the waveform can be suf ficient to trip the comparator resulting in random and pre - mature pulse termination. the addition of a small amount of artificial ramp (slope compensation) can eliminate such problems without drastically af fecting the overall performance of the system. 2.3 circuit layout and other considerations the electronic noise generated by any switch- mode power supply can cause severe stability problems if the circuit is not layed-out (wired) properly . a few simple layout practices will help to minimize noise problems. when building prototype breadboards, never use plug-in protoboards or wire wrap construction. for best results, do all breadboarding on double sided pcb using ground plane techniques. keep all traces and lead lengths to a minimum. a void large loops and keep the area enclosed within any loops to a minimum. use common point grounding techniques and separate the power ground traces from the signal ground traces. locate the control ic and circuitry away from switching devices and magnetics. also, the tim - ing capacitor ? s ground connection must be right at pin 5 as shown in figure 15. these grounding and wiring techniques are very important because the resistance and inductance of the traces are significant enough to generate noise glitches which can disrupt the normal operation of the ic. also, to provide a low impedance path for high frequency noise, v cc and v ref should be decou - pled to ic ground with 0.1 f capacitors. addi - tional decoupling in other sensitive areas may also be necessary . it is very important to locate the decoupling capacitors as close as possible to the circuit being decoupled. as384x current mode controller

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